assembly - How many levels of pipelining can be acomplished with modern CPUs vs GPUs? -

i red in these slides gpus typically have deeper pipelining cpus.

gpus have deeper pipelines (several thousand stages vs 10-20 cpus)

i find more numbers tried googling , wasn't able find any. noticed wikipedia article noted pentium 4 prescott pipelined.

qualitatively speaking, how pipelining can have more 3 levels? considering fetch/decode/execute cycle, that's 3 things? there's multiple functional units, example there more 1 decoders more 1 instruction can decoded @ time? how can more 1 thing red memory @ once?

please remember include numbers regaurding levels of pipelining in answers.

well, let's start end:

how can more 1 thing read memory @ once?

it is. processor 64 bit data bus doesn't read byte @ time memory, reads 8 bytes @ time. besides, decoding instructions isn't limited 1 memory read.

is there's multiple functional units, example there more 1 decoders more 1 instruction can decoded @ time?

some processors may have parallel processing that, doesn't have be. there time processor between memory reads can decode several instructions in time until next memory read can done.

the limiting factor pipeline in processor execution jumps , forth in code. if code run in sequence, pipelines long. processor tries predict execution going, prediction wrong makes rest of work done in pipeline useless.

the code graphics processors executes lot more math , lot less jumping around, can make use of lot longer pipelines.