VHDL - why do we need to declare signals for processes? -

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just revisiting vhdl , wondering inside processes example, why need declare signal clock example? later on in code assign port entity...

example vhdl:

signal clk_int: std_logic := '1';  begin clkgen: process(clk_int) begin clk_int <= not clk_int after 50ns end process ckgen  ck_l <= clk_int;

in example ck_l physcial port d flip flop yet create , mess around clk int return value ck

the reason port ck_l in case declared direction out, cannot read from. if want read it, need if want have process sensitive it, need use signal or declare port inout or buffer.


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